MEMORY ADDRESS TRANSLATION METHOD FOR FLASH STORAGE SYSTEM
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United States of America Patent
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Feb 20, 2014
app pub date -
Aug 18, 2012
filing date -
Aug 18, 2012
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Abstract
A memory address translation method for flash storage system is disclosed. There are two level mapping tables to reduce overhead of mapping table management. In level-one mapping table, each entry contains two kinds of information, which one is the validation of this entry, called Valid Mark and the other is the location of level-two mapping. The level-one mapping table is always located on RAM, and never saved into flash memory. In level-two mapping table, each entry contains two kinds of information, which one is the validation of this entry and the other is the physical location of data in flash memory. The physical addresses of both data and level-two mapping table are dynamically determined. Level-two mapping table is loaded to RAM when it is needed to reference, and is saved into flash memory periodically if the content is updated.
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