Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines

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United States of America Patent

PATENT NO 9245629
APP PUB NO 20140043911A1
SERIAL NO

14057971

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Abstract

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A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.

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Patent Owner(s)

Patent OwnerAddress
SANDISK TECHNOLOGIES INC951 SANDISK DRIVE LEGAL DEP MILPITAS CA 95035

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fasoli, Luca Campbell, US 42 2691
Higashitani, Masaaki Cupertino, US 276 5141
Samachisa, George Atherton, US 89 5998
Scheuerlein, Roy Edwin Cupertino, US 24 2258

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