PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Feb 13, 2014
app pub date -
Sep 14, 2012
filing date -
Aug 8, 2012
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A manufacturing method of a package carrier is provided. An insulation substrate having an upper surface, a lower surface, plural cavities located at the lower surface and plural through holes passing through the insulation substrate and respectively communicating with the cavities is provided. Plural vias is defined by the cavities and the through holes. A conductive material filling up the vias is formed to define plural conductive posts. An insulation layer having a top surface and plural blind vias extending from the top surface to the conductive posts is formed on the upper surface. A patterned circuit layer filling up the blind vias, being connected to the conductive posts and exposing a portion of the top surface is formed on the top surface. A solder mask layer is formed on the patterned circuit layer and has plural openings exposing a portion of the patterned circuit layer to define plural pads.
First Claim
Other Claims data not available