DIGITAL FREQUENCY DEMODULATOR WITH LOW POWER CONSUMPTION AND RELATED SYSTEM AND METHOD
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United States of America Patent
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Issued Date -
Jan 2, 2014
app pub date -
Jun 28, 2012
filing date -
Jun 28, 2012
priority date (Note) -
Abandoned
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Abstract
An apparatus includes a frequency counter configured to receive an input signal containing pulses and to output a count value identifying a number of pulses in the input signal during a specified time period. The specified time period encompasses multiple cycles of the input signal. The apparatus also includes a comparator configured to receive the count value, compare the count value to a second value, and provide an output signal based on the comparison. The apparatus further includes a data latch configured to latch the output signal, where the latched value of the output signal represents a demodulated data value. The comparator could be configured to compare the count value to a fixed value associated with a desired frequency of the input signal. The comparator could also be configured to compare the count value in one specified time period to a stored count value from another specified time period.
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