High-Speed Sensing Scheme for Memory
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Jan 2, 2014
app pub date -
Jun 28, 2012
filing date -
Jun 28, 2012
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A sensing circuit for use in a memory including memory cells and at least one bitline coupled with the memory cells includes first and second sense amplifiers and a controller coupled with the sense amplifiers. The first sense amplifier is adapted to read a selected one of the memory cells coupled to the first sense amplifier via a corresponding bitline. The second sense amplifier is adapted to read a selected one of the memory cells coupled to the second sense amplifier via a corresponding bitline. The controller selectively connects one of the first and second sense amplifiers in an active path of the memory in a manner which enables one of the sense amplifiers to be operative in a precharge mode and another of the sense amplifiers to be concurrently operative in a sensing mode during a given memory cycle.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully