Down-sampling clock and data recovery circuit having selectable rate and phase output and method of operation thereof
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United States of America Patent
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Mar 3, 2015
Grant Date -
Dec 5, 2013
app pub date -
Jun 1, 2012
filing date -
Jun 1, 2012
priority date (Note) -
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Abstract
A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.
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