POWER SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
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United States of America Patent
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Issued Date -
Nov 28, 2013
app pub date -
Nov 22, 2012
filing date -
May 23, 2012
priority date (Note) -
Abandoned
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Abstract
A power semiconductor package and a method of method of manufacturing the same are disclosed, where the power semiconductor package includes a lead frame, a first die, a second die and a single connecting strip. The lead frame includes a voltage plate, a grounding plate, an output plate, a first gate plate and a second gate plate. The first die is disposed on the voltage plate, and a high side transistor within the first die is connected to the first gate plate. The second die is disposed on the grounding plate, and a low side transistor within the second die is connected to the second gate plate. The connecting strip is disposed on the first and second dies and the output plate and electrically connects to a source of the high side transistor and a drain of the low side transistor.
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