MEMORY ELEMENT, STACKING, MEMORY MATRIX AND METHOD FOR OPERATION
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United States of America Patent
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Issued Date -
Nov 14, 2013
app pub date -
Jul 16, 2013
filing date -
May 29, 2009
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Disclosed is a memory element, a stack, and to a memory matrix in which the memory element can be used. Also disclosed is a method for operating the memory matrix, and to a method for determining the true value of a logic operation in an array comprising memory elements. The memory element has at least a first stable state 0 and a second stable state 1. By applying a first write voltage V0, this memory element can be transferred into the high-impedance state 0 and by applying a second write voltage V1, it can be transferred into the likewise high-impedance state 1. By applying a read voltage VR, the magnitude of which is smaller than the write voltages V0 and V1, the memory element exhibits different electrical resistance values. In the parasitic current paths occurring in a memory matrix, the memory element acts as a high-impedance resistor, without in principle being limited to unipolar switching. A method has been disclosed, using an array comprising the memory elements which can be turned into a gate for arbitrary logic operations.

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- 15 United States
- 10 France
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- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
FORSCHUNGSZENTRUM JUELICH GMBH | FACHBEREICH PATENTE JUELICH 52425 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
KUEGELER, Carsten | Oldenburg, DE | 7 | 16 |
LINN, Eike | Aachen, DE | 4 | 12 |
ROSENZIN, Roland Daniel | Bernau, DE | 1 | 0 |
WASER, Rainer | Aachen, DE | 12 | 71 |
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11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | May 14, 2025 |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
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