OPERATION SYSTEM AND CONTROL METHOD THEREOF
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United States of America Patent
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Issued Date -
Nov 7, 2013
app pub date -
Aug 9, 2012
filing date -
May 2, 2012
priority date (Note) -
Abandoned
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Abstract
An operation system including a chipset and a detection unit is disclosed. The chipset includes a first circuit group receiving a plurality of operation voltages. The detection unit generates a control signal to control the first circuit group to stop accessing a memory device when an external power is abnormal. A level of the control signal switches before variation in a level of a first operation voltage among the operation voltages. The variation is induced when the external power is abnormal.
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