COMPACT TID HARDENING NMOS DEVICE AND FABRICATION PROCESS

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United States of America Patent

APP PUB NO 20130285147A1
SERIAL NO

13870860

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Abstract

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A radiation-hardened transistor is formed in a p-type semiconductor body having an active region doped to a first level and surrounded by a dielectric filled shallow trench isolation region. N-type source/drain regions are disposed in the active region and spaced apart to define a channel. A gate is disposed above the channel, and is self-aligned with the source/drain regions. First and second p-type regions are disposed in the p-type semiconductor body on either side of one of the source/drain regions and are doped to a second level higher than the first doping level. The first and second p-type regions are self aligned with and extend outwardly from a first side edge of the gate. The ends of the gate extend past the first and second p-type regions.

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Patent Owner(s)

Patent OwnerAddress
MICROSEMI SOC CORP2355 WEST CHANDLER BOULEVARD CHANDLER AS 85224

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dhaoui, Fethi Mountain House, US 47 383

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