Self-aligned process to fabricate a memory cell array with a surrounding-gate access transistor
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United States of America Patent
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Nov 26, 2013
Grant Date -
Aug 1, 2013
app pub date -
Feb 1, 2012
filing date -
Feb 1, 2012
priority date (Note) -
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Abstract
A memory array including a plurality of memory cells. Each word line is electrically coupled to a set of memory cells, a gate contact and a pair of dielectric pillars positioned parallel to the word line. Dielectric pillars are placed on both sides of the gate contact. Also a method to prevent a gate contact from electrically connecting to a source contact for a plurality of memory cells on a substrate. The method includes formation of a pair of pillars made of an insulating material over the substrate, depositing an electrically conductive gate material between and over the pillars, etching the gate material such that it both partially fills a space between the pair of pillars and forms a word line for the memory cells, and depositing a gate contact between the dielectric pillars such that the gate contact is in electrical contact with the gate material.
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