METHOD OF FORMING SOLDER RESIST LAYER AND PRINTED CIRCUIT BOARD COMPRISING SOLDER RESIST LAYER
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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N/A
Issued Date -
Aug 1, 2013
app pub date -
Feb 1, 2013
filing date -
Feb 3, 2012
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Provided are a method of forming a solder resist layer on a printed circuit board (PCB) and a PCB comprising the solder resist layer. The method includes: preparing a PCB of which at least one surface has a circuit layer formed thereon, bonding an insulation layer, including a material having a non-photosensitive characteristic, in a half-cured state on the circuit layer, forming a solder resist layer patterned by selectively removing the insulation layer, and curing the insulation layer.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
MDS CO LTD | 84 JEONGDONG-RO SEONGSAN-GU GYEONGSANGNAM-DO CHANGWON-SI 641-120 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
KWON, Soon-Chul | Changwon-city, KR | 5 | 12 |
# of filed Patents : 5 Total Citations : 12 | |||
LEE, Sang-Min | Changwon-city, KR | 249 | 5049 |
# of filed Patents : 249 Total Citations : 5049 |
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Patent Citation Ranking
- 3 Citation Count
- H05K Class
- 2.95 % this patent is cited more than
- 12 Age
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11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Feb 1, 2025 |
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