OUTPUT BUFFER CIRCUIT
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United States of America Patent
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Issued Date -
Jul 11, 2013
app pub date -
Sep 20, 2012
filing date -
Oct 14, 2011
priority date (Note) -
Abandoned
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Abstract
There is provided an output buffer circuit which can reduce the time differences of the rise time and fall time of the output voltages of a differential output signal and, furthermore, can make the rise time and fall time match with a good precision. To the resistance elements R1, R2, PMOS transistors Tr5, Tr6 are connected in parallel. At this time, if designating the resistance components of the resistance elements R1, R2 as r1(Ω), r2(Ω), designating the resistance components of the PMOS transistors Tr5, Tr6 as rTr5(Ω) and rTr6(Ω), and designating the resistance component of the current source I1 as rI1(Ω), the conditions of (r1//rTr5)=(r2//rI1) and (r2//rTr6)=(r1//rI1) are satisfied. Due to this, the time differences between the rise time and fall time of the output voltages can be reduced and, furthermore, the rise time and fall time can be made to precisely match.
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