PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE
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United States of America Patent
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Issued Date -
Jul 4, 2013
app pub date -
Nov 1, 2012
filing date -
Dec 28, 2011
priority date (Note) -
Abandoned
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Abstract
Disclosed is a package method for electronic components by a thin substrate, comprising: providing a carrier; forming at least one metal layer and at least one dielectric layer on the carrier for manufacturing the thin substrate, and the thin substrate comprises at least one package unit for connecting at least one chip; forming at least one pad layer on a surface of the thin substrate; parting the thin substrate from the carrier; performing test to the thin substrate to weed out the package unit with defects in the at least one package unit and select the package units for connecting the chips; connecting the chips with the selected package units by flip chip bonding respectively. Accordingly, the yield of the entire package process can be improved and the pointless manufacture material cost can be reduced.
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