METHOD OF FORMING VIA HOLE IN CIRCUIT BOARD
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United States of America Patent
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Issued Date -
Jul 4, 2013
app pub date -
Dec 26, 2012
filing date -
Jan 3, 2012
priority date (Note) -
Abandoned
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Abstract
A method of forming a via hole in a circuit board including an insulating layer and a metal layer disposed on each of top and bottom surfaces of the insulating layer, the method including: selectively removing a portion of each of the metal layers where the via hole is to be formed thereby exposing the insulating layer; and removing the exposed insulating layer, wherein the removing of the exposed insulating layer includes chemically swelling the exposed insulating layer and removing the swollen insulating layer.
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