CURRENT-MODE SAMPLE AND HOLD FOR DEAD TIME CONTROL OF SWITCHED MODE REGULATORS
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United States of America Patent
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Issued Date -
Jun 20, 2013
app pub date -
Dec 19, 2012
filing date -
Dec 20, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A system for current mode sample and hold, comprising a first PMOS transistor configured to generate a current to be sampled. A diode-connected NMOS transistor coupled to the first PMOS transistor and configured to receive the current. A switch coupled to the diode-connected NMOS transistor and configured to sample a gate-source voltage of the diode-connected NMOS transistor. A capacitor coupled to the switch and configured to stored the gate-source voltage of the diode-connected NMOS transistor. A second NMOS transistor coupled to the capacitor and configured to generate a current equal to the sampled current value.
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