METHOD FOR SUPPRESSING KIRKENDALL VOIDS FORMATION AT THE INTERFACE BETWEEN SOLDER AND COPPER PAD
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United States of America Patent
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app pub date -
Apr 10, 2012
filing date -
Dec 14, 2011
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Abandoned
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Abstract
The embodiment of the present invention relates to a method for suppressing Kirkendall voids formation in a solder joint. A solder alloy doped with 0.1˜0.7 weight percent (wt. %) of palladium (Pd) is utilized. Before soldering, the solder alloy is disposed on a copper (Cu) pad, possibly treated with a surface finish. Subsequently, the solder alloy is joined with the Cu pad, so as to form the solder joint with a Cu/Cu3Sn/(Cu,Pd)6Sn5/solder structure. The formation of Kirkendall voids at the Cu/Cu3Sn interface is greatly suppressed in the presence of Pd in the solder. As the amount of Pd doped is minimal, the properties and the processing conditions for soldering are not changed to a large extent, and the mechanical reliability of the solder joint is significantly improved. Therefore, the present invention is suitable for the microelectronic packaging applications.
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