MOS TRANSISTOR USING STRESS CONCENTRATION EFFECT FOR ENHANCING STRESS IN CHANNEL AREA
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United States of America Patent
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Issued Date -
May 30, 2013
app pub date -
Apr 22, 2011
filing date -
Jul 15, 2010
priority date (Note) -
Abandoned
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Abstract
A MOS transistor (60, 62) is provided. The structure of the transistor (60, 62) includes: a semiconductor substrate (10), a channel area (20, 24), source/drain regions (22, 26), a gate (30, 32), a gate insulating layer (11), a shallow trench isolation region (12), a passive layer (50, 52), and holes (40, 42) formed with a certain distance to the gate insulating layer (11). Wherein both the shapes of the holes (40, 42) and the Young's modulus' difference between the material in the holes (40, 42) and that around the holes (40, 42) contribute to the stress concentration effect, thus the stress in the channel area (20, 24) is enhanced. The structure of the transistor (60, 62) can greatly reduce the stress attenuation during the transmission from stress resource to the sensitive region, and concentrate the stress in the sensitive region. The structure can be involved in large size device, especially.
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