SURFACE MOUNT TECHNOLOGY PROCESS FOR ADVANCED QUAD FLAT NO-LEAD PACKAGE PROCESS AND STENCIL USED THEREWITH
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United States of America Patent
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Issued Date -
May 30, 2013
app pub date -
Nov 28, 2011
filing date -
Nov 28, 2011
priority date (Note) -
Abandoned
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Abstract
The invention provides a surface mount technology process for an advanced quad flat no-lead package process and a stencil used therewith. The surface mount technology process for an advanced quad flat no-lead package includes providing a printed circuit board. A stencil with first openings is mounted over the printed circuit board. A solder paste is printed passing the first openings to form first solder paste patterns. The stencil is taken off. A component placement process is performed to place the advanced quad flat no-lead package comprising a die pad on the printed circuit board, wherein the first solder paste patterns contact a lower surface of the die pad, and an area ratio of the first openings to the lower surface of the die pad is between 1:2 and 1:10. A reflow process is performed to melt the first solder paste patterns to surround a sidewall of the die pad.
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