MATRICES FOR RAPID ALIGNMENT OF GRAPHITIC STRUCTURES FOR STACKED CHIP COOLING APPLICATIONS
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United States of America Patent
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Issued Date -
May 23, 2013
app pub date -
Nov 17, 2011
filing date -
Nov 17, 2011
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Abstract
The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip and a second chip electrically and mechanically coupled by a grid of connectors. The chip stack includes a thermal interface material (TIM) between the first chip and the second chip. The TIM includes nanofibers aligned parallel to mating surfaces of the first and second chips, and a thermosetting polymer that when heated, will reduce the viscosity of the TIM to allow for optimal alignment of the carbon nanofibers. The method includes adding at least one thermosetting polymer to the TIM, dispersing nanofibers into the TIM, and heating the TIM until the thermosetting polymer un-crosslinks. The method further includes applying a magnetic field to align the graphite nanofibers and cooling the TIM until the thermosetting polymer re-crosslinks.
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