NON-VOLATILE MEMORY UNIT CELL WITH IMPROVED SENSING MARGIN AND RELIABILITY
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United States of America Patent
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app pub date -
Dec 12, 2012
filing date -
Mar 30, 2010
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Abandoned
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Abstract
A non-volatile memory unit cell includes a transistor pair, and first, second, third and fourth control gates. The transistor pair has a first transistor and a second transistor that are connected in parallel and of opposite types. The first transistor and the second transistor have a first floating polysilicon gate and a second floating polysilicon gate, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated. The first control gate is capacitively coupled to the first floating polysilicon gate through a first coupling junction. The second control gate is capacitively coupled to the second floating polysilicon gates through a second coupling junction. The third control gate is capacitively coupled to the first floating polysilicon gate through a first tunneling junction. The fourth control gate is capacitively coupled to the second floating polysilicon gates through a second tunneling junction.
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