Stacked Semiconductor Package
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United States of America Patent
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Issued Date -
Apr 25, 2013
app pub date -
Jun 15, 2011
filing date -
Jun 22, 2010
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Provided is a stacked semiconductor package. The present invention includes: a substrate having first and second connective pads provided on an upper surface thereof; a first cascade chip laminate which is loaded on the substrate and in which a plurality of first semiconductor chips are stacked in multiple stages to externally expose a first bonding pad wire-bonded through the first connective pad and a first conductive wire; a second cascade chip laminate in which a plurality of second semiconductor chips are stacked in the multiple stages to externally expose a second bonding pad wire-bonded through the second connective pad and a second conductive wire to an area corresponding to the first bonding pad; and a joint part for joining the first cascade chip laminate and the second cascade chip laminate.
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