STRUCTURE OF SEMICONDUCTOR CHIPS WITH ENHANCED DIE STRENGTH AND A FABRICATION METHOD THEREOF
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Apr 25, 2013
app pub date -
Jan 24, 2012
filing date -
Oct 21, 2011
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
An improved structure of semiconductor chips with enhanced die strength and a fabrication method thereof are disclosed. The improved structure comprises a substrate, an active layer, and a backside metal layer, in which the active layer is formed on the front side of the substrate and includes at least one integrated circuit; the backside metal layer is formed on the backside of the substrate, which fully covers the area corresponding to the area covered by the integrated circuits in the active layer. By using the specific dicing process of the present invention, the backside metal layer and the substrate can be diced tidily. Die cracking on the border between the substrate and the backside metal layer of the diced single chip can be prevented, and thereby the die strength can be significantly enhanced.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully