Layered Semiconductor Package
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United States of America Patent
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Issued Date -
Apr 18, 2013
app pub date -
Jun 1, 2011
filing date -
Jun 22, 2010
priority date (Note) -
Abandoned
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Abstract
Provided is a layered semiconductor package. The present invention comprises: a substrate having a first connection pad and a second connection pad on the upper surface thereof; a first cascade chip-layered body mounted on the substrate in which a plurality of first semiconductor chips are layered in a stepped form so as to expose a first bonding pad to the outside; at least one spacer layered on the upper surface of the uppermost semiconductor chip of the first chip-layered body so as to expose a bonding pad of the uppermost semiconductor chip; a second cascade chip-layered body mounted on the upper surface of the spacer in which a plurality of second semiconductor chips are layered in a stepped form so as to expose a second bonding pad to the outside; a first conductive wire for electrically connecting the first bonding pad of the first semiconductor chip and the first connection pad of the substrate; and a second conductive wire for electrically connecting the second bonding pad of the second semiconductor chip and the second connection pad of the substrate.
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