Circuit test interface and test method thereof
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United States of America Patent
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Apr 22, 2014
Grant Date -
Apr 4, 2013
app pub date -
Oct 4, 2011
filing date -
Oct 4, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.
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