FLASH MEMORY CONTROLLER ADAPTIVELY SELECTING ERROR-CORRECTION SCHEME ACCORDING TO NUMBER OF PROGRAM/ERASE CYCLES OF FLASH MEMORY
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United States of America Patent
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Issued Date -
Mar 28, 2013
app pub date -
Sep 22, 2011
filing date -
Sep 22, 2011
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Abandoned
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Abstract
A flash memory controller includes an encoding block, a decoding block and a control unit. The encoding block is utilized for encoding raw bits with a target forward error-correction (FEC) coding scheme selected from a plurality of candidate FEC coding schemes. The decoding block is utilized for decoding encoded bits with a target FEC decoding scheme selected from a plurality of candidate FEC decoding schemes, wherein the target FEC decoding scheme corresponds to the target FEC coding scheme. The control unit is coupled to the encoding block and the decoding block, and utilized for controlling a selection of the target FEC coding scheme utilized by the encoding block and a selection of the target FEC decoding scheme utilized by the decoding block according to a number of program/erase cycles of a flash memory.
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