TRANSISTOR STRUCTURE AND RELATED TRANSISTOR PACKAGING METHOD THEREOF
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United States of America Patent
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Issued Date -
Mar 14, 2013
app pub date -
Sep 13, 2012
filing date -
Sep 13, 2011
priority date (Note) -
Abandoned
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Abstract
A transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.
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