SOI Semiconductor Structure with a Hybrid of Coplanar Germanium and III-V, and Preparation Method thereof

Number of patents in Portfolio can not be more than 2000

United States of America Patent

APP PUB NO 20130062696A1
SERIAL NO

13636128

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Abstract

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The present invention provides an SOI semiconductor structure with a hybrid of coplanar germanium (Ge) and III-V, and a method for preparing the same. A heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material coplanar on an insulator includes at least one Ge substrate formed on the insulating layer, and the other substrate is a group III-V semiconductor material formed on the Ge semiconductor. The preparation method for forming the semiconductor structure includes: preparing a global Ge on insulator substrate structure; preparing a group III-V semiconductor material layer on the Ge on insulator substrate structure; performing photolithography and etching for the first time to make a patterned window to the above of a Ge layer to form a recess; preparing a spacer in the recess; preparing a Ge film by selective epitaxial growth; performing a chemical mechanical polishing to obtain the heterogeneous integrated semiconductor structure with a hybrid of Ge and the group III-V semiconductor material being coplanar; removing the spacer and a defective Ge layer part close to the spacer; implementing isolation between Ge and the group III-V semiconductor material; and preparing a high-performance CMOS device including a Ge PMOS and a III-V NMOS by forming an MOS structure.

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Patent Owner(s)

Patent OwnerAddress
SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES200050 NO 865 CHANGNING ROAD SHANGHAI CHANGNING DISTRICT SHANGHAI CITY SHANGHAI CITY 200050

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bian, Jiantao Shanghai, CN 6 44
Di, Zengfeng Shanghai, CN 12 61
Wang, Xi Shanghai, CN 356 3114
Zhang, Miao Shanghai, CN 114 550

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