VERSATILE DATA PROCESSOR EMBEDDED IN A MEMORY CONTROLLER
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United States of America Patent
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Issued Date -
Mar 7, 2013
app pub date -
Sep 6, 2012
filing date -
Sep 6, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A first engine and a memory access controller are each configured to receive memory operation information in parallel. In response to receiving the memory operation information, the first engine is prepared to perform a function on memory data associated with the memory operation and the memory controller is configured to prepare the memory to cause the memory operation to be performed.
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