SRAM DIMENSIONED TO PROVIDE BETA RATIO SUPPORTING READ STABILITY AND REDUCED WRITE TIME
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Mar 7, 2013
app pub date -
Aug 24, 2012
filing date -
Sep 2, 2011
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A 6T SRAM includes two inverters connected in antiparallel, and two access transistors, each connected between a bit line and a common node of the inverters. Each inverter includes a pullup transistor and a pulldown transistor. A product formed by a ratio of the pulldown transistor gate width to the access transistor gate width multiplied by a ratio of the access transistor gate length to the pulldown transistor gate length is smaller than one. Furthermore, the pullup transistor gate width is greater than or equal to the pulldown transistor gate width.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully