METHOD OF TESTING STACKED SEMICONDUCTOR DEVICE STRUCTURE
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United States of America Patent
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Issued Date -
Feb 28, 2013
app pub date -
Apr 12, 2012
filing date -
Aug 25, 2011
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Abandoned
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Abstract
The present invention provides a method of testing a stacked semiconductor device structure. This method includes the following steps: providing a testing board having a plurality of testing points and a probe card; providing a substrate which is disposed on the testing board; providing a plurality of semiconductor devices; mounting and electrically connecting a first one of the semiconductor devices onto the substrate; mounting and electrically connecting a second one of the semiconductor devices onto the first one of the semiconductor devices; keeping the probe card in contact with the second one of the semiconductor devices for electrical testing; and repeating the steps of mounting and testing of the semiconductor devices until all of the semiconductor devices are tested. This method can ensure the integrity of electrical interconnections between the semiconductor devices of the stacked structure.
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