Low-dropout linear voltage stabilizing circuit and system
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United States of America Patent
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Issued Date -
Feb 28, 2013
app pub date -
May 17, 2012
filing date -
Aug 30, 2011
priority date (Note) -
Abandoned
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Abstract
A low-dropout linear voltage stabilizing circuit includes a power source terminal, a reference voltage terminal, an outputting terminal, a load and a grounding terminal, a fast channel circuit connected between the power source terminal and the load for adjusting voltage values outputted by the outputting terminal and a slow channel circuit connected between the power source terminal and the load for stabilizing the voltage values outputted by the outputting terminal The fast channel circuit and the slow channel circuit are connected to the outputting terminal The slow channel circuit is connected to the reference voltage terminal. The fast channel circuit comprises a first FET and a controlling subcircuit. The slow channel circuit comprises an operational amplifier connected to the reference voltage terminal, a first resistance, a second resistance connected to the first resistance and the first FET. A low-dropout linear voltage stabilizing system is further provided.
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