CHIP-ON-PACKAGE STRUCTURE FOR MULTIPLE DIE STACKS
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United States of America Patent
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Issued Date -
Jan 17, 2013
app pub date -
Jul 14, 2011
filing date -
Jul 14, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A multi-die semiconductor device is disclosed. The device may include one or more first-sized die on a substrate and one or more second-sized die affixed over the one or more first-sized die. The second-sized die may have a larger footprint than the first-sized die. An internal molding compound may be provided on the substrate having a footprint the same size as the second-sized die. The second-sized die may be supported on the internal molding compound. Thereafter, the first and second-sized die and the internal molding compound may be encapsulated in an external molding compound.
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