STRUCTURE FOR MICROELECTRONICS AND MICROSYSTEM AND MANUFACTURING PROCESS

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United States of America Patent

APP PUB NO 20130012024A1
SERIAL NO

13618697

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Abstract

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A process for making cavities in a multilayer structure by providing a multilayer structure that includes a surface layer, a planar support substrate and a buried layer between the layer and the support substrate, wherein the buried layer comprises areas of first and second materials with the first material having a higher etching rate than the second material; producing an opening in the surface layer that extends to the area(s) of the first material of the buried layer; and etching the first material to form at least one cavity in the buried layer.

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Patent Owner(s)

Patent OwnerAddress
SOITECPARC TECHNOLOGIQUE DES FONTAINES CHEMIN DES FRANQUES BERNIN 38190

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aspar, Bernard St. Ismier, FR 90 4100

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