INTEGRATION OF VERTICAL BJT OR HBT INTO SOI TECHNOLOGY

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United States of America Patent

APP PUB NO 20130001647A1
SERIAL NO

13170473

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Abstract

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In an embodiment, a bipolar transistor structure is formed on a silicon-on-insulator (SOI) structure that includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate and a top silicon layer formed on the buried oxide layer. The bipolar transistor structure includes: an opening formed in the top silicon layer; an opening in the buried oxide layer beneath the opening in the top silicon layer, the opening in the buried oxide layer including a region that undercuts the opening in the top silicon layer at a side of the opening in the top silicon layer; conductive material having a first conductivity type formed in the opening in the buried oxide layer such that the conductive material includes a region that undercuts the top silicon layer at the side of the opening in the top silicon layer; isolation dielectric material formed in the top silicon layer over the region of conductive material that undercuts the top silicon layer to define a bipolar transistor collector region having the first conductivity type, the collector region being in contact with the region of conductive material; a bipolar transistor base region formed in contact with an upper surface of the collector region, the base region having a second conductivity type that is opposite the first conductivity type; and an emitter region formed in contact with the base region, the emitter region having the first conductivity type.

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Patent Owner(s)

Patent OwnerAddress
NATIONAL SEMICONDUCTOR CORPORATION2900 SEMICONDUCTOR DRIVE M/S D3-579 SANTA CLARA CA 95051

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Adler, Steven J Saratoga, US 17 332

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