METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE
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United States of America Patent
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Issued Date -
Nov 8, 2012
app pub date -
Jun 30, 2011
filing date -
May 5, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed.
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