Mold array process method to encapsulate substrate cut edges

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United States of America Patent

PATENT NO 8361841
APP PUB NO 20120270368A1
SERIAL NO

13093476

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Disclosed is a mold array process (MAP) method to encapsulate cut edges of substrate units. A substrate strip includes a plurality of substrate units arranged in a matrix. Scribe lines are defined between adjacent substrate units and at the peripheries of the matrix where pre-cut grooves are formed along the scribe lines with a width greater than the width of the scribe lines. An encapsulant is formed on the matrix of the substrate strip to continuously encapsulate the substrate units and the scribe lines to enable the encapsulant to fill into the pre-cut grooves to further encapsulate the cut edges of the substrate units. The cut edges of the substrate units are still encapsulated by the encapsulant even after singulation processes where substrate units are singulated into individual semiconductor packages to prevent the exposure of the plated traces of the substrate units to enhance the moisture resistance capability of the semiconductor packages.

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Patent Owner(s)

Patent OwnerAddress
WALTON ADVANCED ENGINEERING INCNO 18 NORTH FIRST ROAD K E P Z KAOHSIUNG CITY

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Yung-Hsiang Kaohsiung, TW 186 4204
Chiu, Wen-Chun Kaohsiung, TW 9 112
Lee, Kuo-Yuan Kaohsiung, TW 13 194

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