FAULT TOLERANT REDUNDANT CLOCK CIRCUIT
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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N/A
Issued Date -
Oct 18, 2012
app pub date -
Jun 22, 2012
filing date -
Nov 19, 2008
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.
First Claim
Other Claims data not available