CONTEMPORANEOUS MARGIN VERIFICATION AND MEMORY ACCESS FOR MEMORY CELLS IN CROSS POINT MEMORY ARRAYS

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United States of America Patent

SERIAL NO

13530009

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory elements. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory elements substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory elements may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).

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Patent Owner(s)

Patent OwnerAddress
UNITY SEMICONDUCTOR CORPORATIONSAN JOSE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chevallier, Christophe Palo Alto, US 141 2436
Siau, Chang Hua Saratoga, US 70 1564

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