SEMICONDUCTOR DEVICES WITH LAYOUT CONTROLLED CHANNEL AND ASSOCIATED PROCESSES OF MANUFACTURING
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United States of America Patent
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Issued Date -
Sep 27, 2012
app pub date -
Mar 25, 2011
filing date -
Mar 25, 2011
priority date (Note) -
Abandoned
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Abstract
The present technology is directed generally to processes of forming semiconductor devices (e.g., JFET devices). The semiconductor device comprises a gate region, a source region, a drain region and a channel region having a channel size. The channel size is controlled by adjusting a layout width of the gate region.
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