METHOD AND SYSTEM FOR RESOLVING INTEROPERABILITY OF MULTIPLE TYPES OF DUAL IN-LINE MEMORY MODULES
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United States of America Patent
Stats
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N/A
Issued Date -
Sep 20, 2012
app pub date -
Mar 2, 2012
filing date -
Mar 2, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Systems and methods are described for resolving certain interoperability issues among multiple types of memory modules in the same memory subsystem. The system provides a single data load DIMM for constructing a high density and high speed memory subsystem that supports the standard JEDEC RDIMM interface while presenting a single load to the memory controller. At least one memory module includes one or more DRAM, a bi-directional data buffer and an interface bridge with a conflict resolution block. The interface bridge translates the CAS latency (CL) programming value that a memory controller sends to program the DRAMs, modifies the latency value, and is used for resolving command conflicts between the DRAMs and the memory controller to insure proper operation of the memory subsystem.
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International Classification(s)
- 2012 Application Filing Year
- G06F Class
- 48051 Applications Filed
- 40472 Patents Issued To-Date
- 84.23 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 91 Citation Count
- G06F Class
- 90.32 % this patent is cited more than
- 13 Age