Memory access system and method for optimizing SDRAM bandwidth
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United States of America Patent
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Issued Date -
Sep 20, 2012
app pub date -
Aug 31, 2011
filing date -
Mar 16, 2011
priority date (Note) -
Abandoned
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Abstract
A memory access system for optimizing SDRAM bandwidth includes a memory command processor, and an SDRAM interface and protocol controller. The memory command processor is connected to a memory bus arbiter and data switch circuit for receiving memory access commands outputted by the memory bus arbiter and data switch circuit and converting the memory access commands into reordered SDRAM commands. The SDRAM interface and protocol controller is connected to the memory command processor for receiving and executing the reordered SDRAM commands based on protocol and timing of SDRAM. The memory command processor decodes the memory access commands into general SDRAM commands or alternative SDRAM commands. The memory access commands decoded into alternative SDRAM commands are generated by a specific bus master.
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