Non-volatile memory structure and method for manufacturing the same
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United States of America Patent
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Issued Date -
Sep 6, 2012
app pub date -
Jul 26, 2011
filing date -
Mar 3, 2011
priority date (Note) -
Abandoned
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Abstract
A non-volatile memory structure is disclosed. LDD regions may be optionally formed through an ion implantation using a mask for protection of a gate channel region of an active area. Two gates are apart from each other and disposed on an isolation structure on two sides of a middle region of the active area, respectively. The two gates may be each entirely disposed on the isolation structure or partially to overlap a side portion of the middle region of the active area. A charge-trapping layer and a dielectric layer are formed between the two gates and on the active area to serve for a storage node function. They may be further formed onto all sidewalls of the two gates to serve as spacers. Source/drain regions are formed through ion implantation using a mask for protection of the gates and the charge-trapping layer.
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