Method for Fabricating a Small Footprint Chip-Scale Package and a Device Made from the Method
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United States of America Patent
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Issued Date -
Aug 23, 2012
app pub date -
Feb 17, 2012
filing date -
Feb 21, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method for fabricating an integrated circuit chip-scale package and a device made from the method. One or more IC chips are mounted on a carrier and a stud bump defined on an IC pad. The stud-bumped IC is encapsulated to define a potted assembly layer which is thinned to expose the stud bump. Conductive first traces are defined and coupled to the stud bump to reroute the IC pads. A dielectric layer is provided and vias defined there through to expose the first traces. Electrically conductive second traces are disposed on the dielectric layer surface that are coupled to the first traces to reroute the IC pads to define a chip scale package.
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