Wafer-Scale Emitter Package Including Thermal Vias
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Aug 9, 2012
app pub date -
Oct 7, 2010
filing date -
Oct 7, 2009
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Improved packages for light emitters may be fabricated at the wafer level. The package can be a single device or an array of die. The package includes a thermal via that extends through the thickness of the package substrate. The thermal via may be made of a material possessing a high thermal conductivity. The thermal via may be wider at the package exterior than at the interior to provide heat spreading between the device and its heat sink. The taper angle of the thermal via may be around 45 degrees to match the natural spread of heat in a solid. The thermal via may extend above the package interior, so its height is sufficient to position an emitter placed thereon at one foci of a parabola, where the vertex of the parabola is at the surface of the package substrate from which the thermal via extends.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully