Timing adjustment circuit for a memory interface and method of adjusting timing for memory interface
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United States of America Patent
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Nov 12, 2013
Grant Date -
Jul 26, 2012
app pub date -
Sep 19, 2011
filing date -
Jan 21, 2011
priority date (Note) -
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Abstract
According to one embodiment, a timing adjustment circuit for a memory interface is presented. The circuit is provided with a gate circuit, an original gate signal generation circuit, a high impedance prevention unit, an impedance control unit and a gate leveling circuit. The gate circuit performs gating of a data strobe signal outputted from a memory. The original gate signal generation circuit generates an original gate signal based on information of a read latency and a burst length. The high impedance prevention unit to prevent the data strobe signal from being in a high impedance state. The impedance control unit controls execution and release of operation of the high impedance prevention unit. The gate leveling circuit outputs a timing adjusted gate signal to the gate circuit based on the original gate signal and the data strobe signal.
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