Tamper-Resistant Memory Device With Variable Data Transmission Rate
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United States of America Patent
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Issued Date -
Jul 19, 2012
app pub date -
Feb 1, 2012
filing date -
Aug 4, 2010
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A high capacity, secure and tamper-resistant computer data memory device. The device uses a plurality of dedicated memory controller elements in communication with an anti-tamper module that generates a tamper response when a predetermined tamper event occurs. The tamper response may be provided as the erasure or zeroization of the contents of a memory in the devices such as erasing one or more encryption keys. The elements of the device are preferably provided in a stacked configuration with rerouted I/O pads to obfuscate the I/O and function of the devices in the stack. In one embodiment, a data transfer governance means is provided. In a further embodiment, a current negotiation means is disclosed to permit the device to request a predetermined current from a host device. In a yet further embodiment, a portable safe house computing device is provided.
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