SEMICONDUCTOR SURROUND GATE SRAM STORAGE DEVICE
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United States of America Patent
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Issued Date -
Jul 19, 2012
app pub date -
Mar 12, 2012
filing date -
Jan 29, 2008
priority date (Note) -
Abandoned
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Abstract
It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer, and each of the load resistor elements is made of polysilicon and formed on the planar silicon layer.
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