VERTICAL PARASITIC PNP DEVICE IN A SILICON-GERMANIUM HBT PROCESS AND MANUFACTURING METHOD OF THE SAME
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United States of America Patent
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Issued Date -
Jul 19, 2012
app pub date -
Dec 19, 2011
filing date -
Jan 13, 2011
priority date (Note) -
Abandoned
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Abstract
A vertical parasitic PNP device in a SiGe HBT process is disclosed which comprises a collector region, a base region, an emitter region, P-type pseudo buried layers and N-type polysilicons. The pseudo buried layers are formed at bottom of shallow trench field oxide regions around the collector region and contact with the collector region; deep hole contacts are formed on top of the pseudo buried layers to pick up collector electrodes. The N-type polysilicons are formed on top of the base region and are used to pick up base electrodes. The emitter region comprises a P-type SiGe epitaxial layer and a P-type polysilicon both of which are formed on top of the base region. A manufacturing method of a vertical parasitic PNP device in a SiGe HBT process is also disclosed.
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