METHOD FOR FABRICATING TRENCH DMOS TRANSISTOR

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United States of America Patent

SERIAL NO

13394679

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Abstract

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A method for fabricating trench DMOS transistor includes: forming an oxide layer and a barrier layer with photolithography layout sequentially on a semiconductor substrate; etching the oxide layer and the semiconductor substrate with the barrier layer as a mask to form a trench; forming a gate oxide layer on the inner wall of the trench; forming a polysilicon layer on the barrier layer, filling up the trench; etching back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer to form a trench gate; removing the barrier layer and the oxide layer; implanting ions into the semiconductor substrate on both sides of the trench gate to form a diffusion layer; coating a photoresist layer on the diffusion layer and defining a source/drain layout thereon; implanting ions into the diffusion layer based on the source/drain layout with the photoresist layer mask to form the source/drain; forming sidewalls on both the sides of the trench gate after removing the photoresist layer; and forming a metal silicide layer on the diffusion layer and the trench gate. Effective result of the present invention is achieved with lower cost and improved efficiency of fabrication.

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Patent Owner(s)

Patent OwnerAddress
CSMC TECHNOLOGIES FAB1 CO LTDNO 8 XINZHOU ROAD WUXI NEW DISTRICT JIANGSU 214028
CSMC TECHNOLOGIES FAB2 CO LTD214028 NO 8 XINZHOU ROAD NATIONAL HI TECH INDUSTRIAL DEVELOPMENT ZONE WUXI JIANGSU WUXI CITY JIANGSU PROVINCE 214028

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Wang, Le Wuxi, CN 234 1886

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